Many advanced silicon-based microdevices incorporate alternative micro components, such as mechanical, optical, chemical, biological and other types of physical components, with basic microelectronic devices on one silicon substrate, and the silicon substrate could be described as a silicon wafer. And many of such alternative micro components need to be encapsulated in micro to nano scale cavities forming on top of the silicon substrate. Furthermore, such microdevices are preferably fabricated through a unified wafer level fabrication process on the same silicon substrate, from forming microelectronic devices and alternative micro components to forming and encapsulating the micro or nano cavities.
Meanwhile, electrical in-out pads in such microdevices for electrical signal and power transmission with such microdevices, produced on the one side of the silicon substrate, are preferably rerouted to the opposite side of the silicon substrate through so-called through-silicon via interconnects, for reducing the planar size of the microdevices while making ease for encapsulation and cavity formation and if necessary, enabling 3-dimensional packaging by bonding and stacking another silicon substrate. Due to substantial mechanical handling and potential damage issues on such a silicon wafer on the top side of which microelectronic and alternative micro components, containing micro to nano scale cavities, are readily formed, further fabricating through-silicon via interconnects to the bottom side and meanwhile encapsulating the top side of the silicon wafer is substantially difficult and still remains of substantial issues in the prior art.
Therefore robust and practical wafer level fabrication methods are desired for non-invasively forming through-silicon via from the backside of a silicon wafer and encapsulation of the microelectronic and alternative micro components previously fabricated on the top side of the silicon wafer. One typical class of such methods includes the following basic sequential steps: 1) first mechanically attaching a protective film, for example a resin film, onto the micro components upon fabrication on the top side of the silicon wafer; 2) processing the through-silicon via and interconnects from the back side of the silicon wafer; 3) mechanically detaching the protective film attaching on the top side; and 4) encapsulating the micro components on the top side of the silicon wafer. Such basic method of this class is widely used for backside grinding and thinning of conventional semiconductor wafers upon fabricating microelectronic devices on the top side. However the mechanical attachment and detachment of the protective film relative to the top side of the silicon wafer, containing alternative micro components to the conventional microelectronic devices, lead in many cases to inevitable mechanical damage and chemical contamination to those micro components. In particular, any MEMS components suspended above cavities are considerably vulnerable to such mechanical attachment and detachment of such protective film.
Another class of such methods in the prior art consists of the following sequential steps: 1) first encapsulating the micro components and the top side of the silicon wafer; and 2) producing the through-silicon via and interconnects from the backside of the silicon wafer. Although this would provide physical protection of the fabricated micro components on the top side from potential mechanical damage and chemical contamination during the backside thinning and fabrication of through-silicon via and interconnects, dramatic increase in the wafer stack thickness, typically 2 times the standard silicon wafer thickness, would lead to the wafer handling issue during the backside wafer processing for thinning and through-silicon via formation. If the top encapsulation is very delicate for particular optical consideration, such an extensive backside wafer processing remains as an issue at stake among others.